The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type field-effect transistors (pFETs) and n-type field-effect transistors (nFETs) that are coupled to implement logic gates and other types of integrated circuits, such as switches. Field-effect transistors generally include a body region, a source and a drain defined in the body region, and a gate electrode associated with a channel in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current.
Silicon-on-insulator (SOI) substrates may be advantageous in CMOS technology. In comparison with field-effect transistors built using a bulk silicon wafer, a silicon-on-insulator substrate permits field-effect transistors to operate at significantly higher speeds with improved electrical isolation and reduced electrical losses. Contingent on the thickness of a device layer of the SOI substrate, a field-effect transistor may operate in a partially-depleted mode in which the depletion layer in the channel within the body region does not extend fully to the buried oxide layer when typical control voltages are applied to the gate electrode.
Improved device structures for a field-effect transistor and methods for forming a device structure for a field-effect transistor are needed.